Smart Stacking is a unique technology that enables very thin layers of partially or fully CMOS processed wafers to be transferred onto other wafers.
This is done through low-temperature direct wafer bonding and mechanical-chemical thinning to offer a wide range of layer transfer capabilities to address customers’ specific needs.
This scalable technology is suitable for wafer diameters from 150mm to 300mm and is compatible with various substrate types including silicon, glass, ceramics (polycrystalline AlN), fused silica and sapphire.
Soitec’s Smart Stacking technology entails transferring thin wafer-level layers onto other substrates. The technology can be rolled out in a high-throughput, high-quality manufacturing environment.
It is supported by more than 20 years of substrate engineering expertise and a strong worldwide IP portfolio.
Direct bonding and thinning:
- Low stress and defect free bonding
- High bonding strength and quality
- Wafer-to-wafer alignment within +/-1μm
- High surface quality
- Improved edge exclusion management
Smart Stacking is compatible with fully-processed wafers as well as partially-processed wafers or wafers with cavities.
The thickness of the transferred layer can range from just a few microns to several hundred microns.
Each process step - surface preparation, wafer bonding, thinning, edge treatment, cleaning and metrology - is optimized based on existing standard semiconductor tools.
The technology is based on existing semiconductor standard tools, resulting in high yield and compliance with reliability standards (for example, it meets military-standard reliability requirements).
We provide technologies suitable for advanced semiconductor applications such as RF products, back-side illuminated (BSI) image sensors, MEMS, and 3D ICs.
From product development to delivery of prototyping and support for high-volume manufacturing, Soitec has the capabilities to offer flexible 3D integration solutions.
We have the expertise, intellectual property, processes, technology and equipment to offer solutions for a broad range of applications.
It also has been widely used in leading smartphones to manufacture high-performance RF switches based on bonded Silicon on Sapphire (BSOS). This technology can dramatically improves the performance of RF products, and is opening new doors to future RF, MEMS and 3D-integration applications.
The process accommodates a very wide range of customer specifications and evolving product design requirements.
In back side illuminated (BSI) image sensors, Smart Stacking is used to bond and thin the processed imager wafer carrying the CMOS sensor circuitry, and expose the back-side of the sensor. It is also perfectly suited for building substrates with embedded cavities or custom 3D structures.