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Soitec processed wafer stacking for 3D integration
Technical capabilities
- Using our Smart Stacking™ technology: direct bonding and thinning techniques
- 150mm and 200mm
- 300mm bonding module
- High- and low-temperature bonding process capabilities
- Partially-processed incoming wafers (including implanted and patterned oxide)
- Fully-processed incoming wafers (CMOS, CCD, Al and Cu interconnect)
- Incoming metrology (topology, surface quality, and global morphology)
- Dedicated manufacturing lines
Benefits for Back Side Illuminated (BSI) image sensors
For Back Side Illuminated (BSI) image sensors, Smart Stacking technology is used to bond and thin the processed imager wafer with CMOS sensor circuitry, exposing the back side of the sensor. Our Smart Stacking technology for image sensors provides:
- Low-stress bonding compatible with advanced color filter arrays.
- High-quality transferred circuits:
- Low bonding defects
- Improved edge exclusion management
- High bonding strength
- Proven reliability to military specifications
- Proven industrial technology for fast ramp-up
Benefits for MEMS applications
Our Smart Stacking technology is perfectly suitable for building substrates with embedded cavities and provides:
- Defect-free bonding
- High surface quality
- High interface quality
- Improved yield
- Reduced cost
Benefits for 3D applications
- Our Smart Stacking technology can be used to build custom 3D structures: Wafer-to-wafer with alignment +/- 1μm
- Oxide-to-oxide or oxide-to-silicon bonding
- Metal-to-metal bonding (under development)
Applications
- Image Sensors
- RF components
- M(O)EMS
- Memory
Target markets
- Consumer and mobile
- Medical
- Automotive
- Computer