Publications
17-Sep-2009White paper - Smart Stacking™ (pdf / 254 Ko)
A Wafer-stacking Technology Platform
by Dr. Bernard Aspar (Vice President, Tracit BU), Dr. Ian Cayrefourcq (Director
Technology Applications, Soitec) and Dr. Jocelyne Wasselin (VP Business Development, Soitec)
01-Jul-2006White paper - Strained Silicon on Insulator (pdf / 376 Ko)
A quick guide to the technology, the processes, the products
by George Celler (Chief Scientist, Soitec USA) and Ian Cayrefourcq (Manager, New Technology Development Dept., Soitec)
01-Jul-2003White paper - Smart Cut™ (pdf / 396 Ko)
A guide to the technology, the process, the products
by George Celler (Chief Scientist, Soitec USA) and Michael Wolf (Sr. VP, Sales & Marketing, Soitec)
01-May-2003Frontiers of silicon-on-insulator (pdf / 1252 Ko)
by George Celler (Chief Scientist, Soitec USA) and Sorin Cristoloveanu
[Journal of Applied Physics]
Copyright (2003) American Institute of Physics. This article may be downloaded for personal use only. Any other use requires prior permission of the author and the American Institute of Physics.